1. Field of the Invention
The present invention relates generally to the design of buffers providing constant voltage, and also to its application in the design and implementation of a multi-stage ADC.
2. Related Art
Buffer amplifier circuits (buffer) are often employed to provide a desired constant reference voltage. In general, a buffer receives a constant voltage from a constant voltage source such as band-gap reference, and generates a reference voltage with a desired drive specification (characteristics of the signal generated by the buffer, such as, signal settling time, magnitude of current provided, noise margin, etc.). The drive specification is generally determined from the expected load and its characteristics offered to the buffer.
The load offered to a buffer varies dynamically with respect to time in several environments. One problem with such varying load is that the reference voltage itself may vary due to the variation in the load. However, the buffer can be designed to settle to the desired reference voltage over time. There are several environments in which such settling duration needs to be short as described with reference to an analog to digital converter (ADC) below.
FIG. 1 is a block diagram of a pipeline ADC in one embodiment illustrating the need for a reference voltage which needs to settle to a desired magnitude within a short duration. ADC 100 is shown containing sample and hold amplifier (SHA) 110, stages 120-1 through 120-S, digital error correction block 130 and reference buffer 150. Each block is described below in further detail.
Reference buffer 150 generates a reference voltage (Vref) on path 152 typically from a constant DC voltage (e.g., bandgap reference voltage, well known in the relevant arts). The reference voltage can be in differential and/or single ended form depending on the requirements of the other components using the voltage. In order to avoid obscuring the features of the present invention, the description henceforth is provided with reference to single ended implementations. The extension of the approaches to differential circuits will be apparent to one skilled in the relevant arts by reading the disclosure provided herein, and such implementations are contemplated to be covered by various aspects of the present invention.
SHA 110 samples the input analog signal received on path 101 and holds the voltage level of the sample on path 111 for further processing. Digital error correction block 130 receives sub-codes from various stages (on paths 123-1 through 123-S respectively), and generates a digital code corresponding to the sample received on path 101. Various error correction approaches, well known in the relevant arts, may be used to correct any errors in the received sub-codes. The generated digital code is provided on path 139 as a final digital code corresponding to the voltage of a sample on the input analog signal at a particular time instant.
Each stage 120-1 through 120-S generates a sub-code (based on the reference signal Vref received on path 152) corresponding to a voltage level of an analog signal received as an input, and an amplified residue signal as an input to a (any) next stage. For example, stage 120-1 converts a voltage level on path 111 to generate a sub-code on path 123-1, and the amplified residue signal generated on path 112 is provided as an input to stage 120-2. A common reference signal Vref is provided to stages 120-1 through 120-S. FIG. 2 further illustrates (logical) components contained in each stage (described with reference to stage 120-1 only, for conciseness) of a pipe line ADC according to a known approach.
With respect to FIG. 2, stage 120-1 is shown containing flash ADC 250, digital to analog converter (DAC) 260, subtractor 270 and gain amplifier 280. Flash ADC 250 (an example of a quantizer) converts a sample of an analog signal received on path 111 into a corresponding p-bit sub-code provided on path 256 (contained in path 123-1 of FIG. 1, and P is less than N). DAC 260 converts the sub-code received on path 256 into corresponding analog signal (Vdac) on path 267.
Subtractor 270 generates a residue signal as the difference of sample 111 (Vi) and the analog signal received on path 267. Gain amplifier 280 amplifies the residue signal (Vi-Vdac) and is provided on path 112 as an amplified residue signal. The signal on path 112 is used to resolve the remaining bits in the N-bit digital code by the subsequent stages of the ADC. The manner in which the residue signal is generated by each stage is described below with respect to FIGS. 3A and 3B.
FIG. 3A is a circuit diagram illustrating the manner in which DAC 260, subtractor 270, and gain amplifier 280 are implemented in an embodiment providing p-bit sub-codes and FIG. 3B is a timing diagram used to illustrate the sample and hold phases of the circuit. The circuit diagram is shown containing op-amp 350, feedback capacitor 360, feedback switch 380 and circuit portions 301-1 through 301-2n. Circuit portions 301-1 is shown containing sampling capacitor 330-1, switch 310A-1, 310B-1 and 310C-1. The remaining circuit portions 310-2 through 310-2n may also contain similar components, and are not described in the interest of conciseness. Each component is described below in further details.
The circuit in FIG. 3A operates using two phase signals, shown as sampling phase 370 and hold phase 390. In the first phase (sampling phase 370) switches 310A-1 through 310A-2n are closed at time points 371 and the remaining switches 380, 310B-1 through 310B-2n, and 310C-1 through 310C-2n are kept open. As a result, each sampling (input) capacitor 330-1 through 330-2n is ideally charged (in duration between 371–372) to the voltage of input sample received on path 111 by time point 372.
In the second phase (between durations 391–392), feedback switch 380 is closed and switches 310A-1 through 310A-2n are kept open. Connections of switches 310B-1 through 310B-2n, and 310C-1 through 310C-2n are made such that the input terminals of each sampling capacitors 330-1 through 330-2n is connected either to Vref or to REFCM terminal, as determined from the output of flash ADC 250. As a result, capacitors 330-1 through 330-2n transfers a charge proportional to the difference (residue) of input signal and the Vref or REFCM to feedback capacitor 360 (up to time point 392). The residue is amplified by op-amp 350 and provided as amplified residue signal to the next stage, as desired.
By examining the operation of the circuit, it may be appreciated that the magnitude of load offered during different hold phases (at every rising edge 391 to reference buffer 150 by the switched capacitor circuit of FIG. 3A) may be different (depending on the value of the sub-code). In particular, the capacitive load offered by the switched capacitor circuit (in durations 391–392) of FIG. 3A is given as:CL=C1(Vref−Vin)/Vref  Equation (1)
wherein Cn represents the capacitance value of all the capacitors connected to Vref, and Vin represents the sampled input voltage.
From Equation 1, it may be appreciated that one factor contributing to load variation is the varying voltage level (Vin) of the input signal. Another factor contributing to load variation is the number of capacitors connected to Vref (buffer 150 in the hold phase), which depends on the output of the quantizer (flash ADC 250). For example during hold phase(s) (between time points 391 and 392 of FIG. 3B), a selected number of sampling capacitors (based on the sub-code) are connected to the Vref and remaining capacitors are connected to REFCM terminal.
Accordingly, when the input signal equals Vref, the capacitive load offered by switched capacitor circuit of FIG. 3A may equal zero. Similarly, when the input signal has voltage level of 0, no capacitor is connected to Vref (since sub-code equals zero), thereby resulting again in zero capacitive load. However, when the input signal is between 0 and Vref, the capacitive load exhibits a quadratic relation with the input signal.
Due to such varying load, the effective reference voltage provided to switched capacitor amplifier circuit may be different in different conversion cycles (in hold phases in particular). One problem with such differences is, the generated digital codes could be non-linear (i.e., the generated code would not be proportionate to the voltage level of the input signal). Such non-linearity is often undesirable.
One known approach to reducing such non-linearity is to design reference buffer 150 to provide a charging current to charge load capacitors connected to the reference buffer (in this case, some of the capacitors 330-1 through 330-2n based on quantizer output) to a desired reference voltage before occurrence of time point 392 in every hold phase.
However, at least for a high frequency operation of ADCs, it is generally desirable to keep the hold phase (391–392) short. Furthermore, the magnitude of the reference voltage provided to the capacitors needs to consistently equal a desired reference value before each edge 392. Such high frequency and accuracy can be attained by providing sufficient amount of current to capacitors 330-1 through 330-2n instantaneously (or in short duration).
In one prior embodiment, such instantaneous current requirement is supported by connecting an external capacitor having a large value at the output of the reference buffer as illustrated in FIG. 4. The circuit shown there contains buffer 410, (large) capacitor 430, sampling capacitor 460 (representing the capacitive load offered by the switched capacitor amplifier of FIG. 3A, in the illustrative example above), resistor 470, and switches 481 and 482. Each component is described below in further detail.
Switches 481 and 482 connect sampling capacitor 460 to an input signal during sampling phase (371–372), and to reference signal/voltage during hold phase (391–392) respectively. Resistor 470 represents an output impedance of reference buffer 410. A voltage drop across the resistor 470 represents the droop (difference in the reference voltage offered between a no-load scenario and when a load is offered). The droop (voltage drop across resistor 470) increases with current drawn from buffer 410.
Large capacitor 430 is connected to the output of the reference buffer 410 (after output impedance 470). The large capacitor is charged (as shown by charging path 413) when load (sampling capacitor 460) is not connected (between time point 371 and 372) to the buffer. During hold phase, the required instantaneous current is supplied by the large capacitor (as shown by path 436) to sampling capacitor 460 (load). Thus, the buffer may merely need to provide an average charging current in the combination of sampling and hold phases to support the charge requirement of the external capacitor.
One recognised problem with the above approach is that the external (fabricated on a different die) capacitor is often connected to the switching load through a bond-pad (connecting interface), which generally offers an inductive impedance. Thus at higher conversion rate, the inductive impendence inhibits instantaneous current from external reference cap. Hence, such an approach may not be suitable for higher conversion rate switched capacitor data converters.
To overcome some of the related problems of the above approach, the large capacitor is built within (integrated into) the reference buffer output stage. However, the large size of the capacitors may present challenges in fabrication. The challenge may be appreciated by recognizing that an ADC generating N bit digital codes may require an internal capacitor having a capacitance of (CLOAD*2N), wherein CLOAD represents the total capacitive load. The total capacitive load is also proportion to 2N, and thus the required capacitance value increases rapidly with increased resolution (increasing N) requirements, and may be practically difficult to fabricate for sufficiently high value of N.
Therefore, what is needed is a method and apparatus which provides a reference voltage with desired accuracy in a short duration to a dynamically varying load.
In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit (s) in the corresponding reference number.